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Chiplet Physical Design Engineer
Исключительная вакансия в одной из самых перспективных компаний в сфере ИИ-железа под руководством легенд индустрии. Предлагает работу с передовыми технологиями (RISC-V, 3nm, Chiplets) и очень конкурентную компенсацию, хотя и с жесткими требованиями к гражданству/статусу.
Сложность вакансии
Роль требует исключительной квалификации: более 10 лет опыта, владение техпроцессами 3нм и ниже, а также глубокие знания в области Chiplet и SiP. Высокая сложность обусловлена необходимостью работы с multi-GHz дизайнами и жесткими требованиями экспортного контроля США.
Анализ зарплаты
Указанный диапазон $100k - $500k крайне широк, так как охватывает позиции от Junior до Principal. Для Senior-уровня в США медиана рынка составляет около $220k-$280k (Total Compensation), что полностью соответствует середине предложенного компанией диапазона.
Сопроводительное письмо
I am writing to express my strong interest in the Senior Chiplet Physical Design Engineer position at Tenstorrent. With over a decade of experience in physical design for high-performance processors and a deep expertise in advanced process nodes, I am excited by Tenstorrent's mission to revolutionize AI computing through RISC-V and chiplet-based architectures. My background in synthesis, place-and-route, and timing closure for multi-GHz designs aligns perfectly with the technical challenges described in this role.
Throughout my career, I have consistently delivered high-quality silicon by mastering Synopsys and Cadence toolsets and developing robust TCL and Python scripts to optimize design flows. I have a proven track record of achieving aggressive PPA targets and navigating the complexities of design closure at 3nm and below. I am particularly drawn to Tenstorrent's collaborative culture and the opportunity to work on System-in-Package (SiP) solutions that integrate multiple chiplets, as I believe this is the future of scalable AI hardware.
I am confident that my technical depth and experience in mentoring global teams will allow me to make immediate contributions to your high-profile programs. I look forward to the possibility of discussing how my skills can help Tenstorrent continue to lead the industry in AI technology.
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Описание вакансии
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.
As a Senior Chiplet Physical Design Engineer at Tenstorrent, you will work on a high-profile, cutting-edge program designing and integrating multiple chiplets into a System-in-Package (SiP). You’ll collaborate closely with Tenstorrent experts and leaders across the USA, Japan, and other global sites, as well as external partners, to deliver world-class CPU and AI silicon. In this role, you will own critical aspects of synthesis and place-and-route for high-speed CPU core designs, contributing directly to performance, power, and area outcomes on advanced process nodes.
This role isremote, based out of The United States.
We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.
Who You Are
- An experienced physical design engineer who thrives in complex, multi-stakeholder projects.
- Detail-driven, with a strong sense of ownership from synthesis through design closure.
- Comfortable working at advanced nodes (3nm and below) and multi-GHz designs.
- A collaborative team player who enjoys mentoring others and influencing methodology.
- Clear communicator who can balance technical depth with schedule and resource constraints.
What We Need
- Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or Computer Science.
- 10+ years of industry experience in physical design for CPU, or GPU products.
- Strong hands-on experience with Synopsys and/or Cadence tools across synthesis, P&R, and closure.
- Proven expertise in timing closure, ECO flows, and PV convergence at block and chip level.
- Proficiency in scripting (TCL required; Python or similar strongly preferred) and strong English communication skills.
What You Will Learn
- How large-scale chiplet-based systems are architected, implemented, and integrated into SiP solutions.
- Best practices for achieving timing and power convergence on advanced silicon technologies.
- How physical design decisions impact system-level performance and scalability.
- Effective collaboration across global teams and external partners.
- How Tenstorrent evolves and standardizes physical design methodologies across projects.
Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.
Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.
This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.
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Навыки
- Python
- TCL
- SIP
- Cadence
- Synthesis
- Physical Design
- Place and Route
- Synopsys
- Timing Closure
- RISC-V
- Chiplet
- 3nm
- ECO flows
- PV convergence
Возможные вопросы на собеседовании
Проверка опыта работы с самыми современными технологическими нормами, упомянутыми в вакансии.
С какими основными проблемами целостности сигналов и электромиграции вы сталкивались при работе с техпроцессами 3нм и ниже?
Вакансия сфокусирована на чиплетах, что требует понимания специфики межсоединений.
Опишите ваш опыт проектирования интерфейсов физического уровня для межчиплетного взаимодействия (например, UCIe или BoW).
Для Senior-позиции критически важно умение автоматизировать сложные процессы.
Приведите пример сложного сценария на TCL или Python, который вы разработали для оптимизации потока проектирования (flow) или закрытия таймингов.
Работа предполагает достижение высоких показателей производительности и энергоэффективности.
Какие стратегии вы используете для достижения сходимости по таймингам (timing closure) в дизайнах с частотой выше 2 ГГц?
Роль подразумевает интеграцию нескольких кристаллов в одну упаковку.
В чем заключаются ключевые отличия в иерархическом планировании (floorplanning) для традиционных монолитных чипов и для систем в корпусе (SiP)?
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