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Senior Staff Engineer, DTCO
Это позиция высшего уровня в одной из ведущих мировых технологических компаний с очень конкурентной заработной платой. Работа в Logic Pathfinding Lab предлагает уникальную возможность участвовать в разработке технологий будущего, хотя и требует обязательного присутствия в офисе в Сан-Хосе.
Сложность вакансии
Роль требует исключительной квалификации: ученой степени PhD и более 10 лет опыта в узкоспециализированной области DTCO. Кандидат должен обладать глубокими знаниями в физике полупроводников, архитектуре ячеек и процессах проектирования чипов на уровне ниже 2 нм.
Анализ зарплаты
Предлагаемый диапазон $189k – $301k полностью соответствует рыночным стандартам для позиций уровня Senior Staff / Principal Engineer в Кремниевой долине. Верхняя граница диапазона является весьма привлекательной даже для высококонкурентного рынка Сан-Хосе.
Сопроводительное письмо
I am writing to express my strong interest in the Senior Staff Engineer, DTCO position at Samsung Semiconductor's Logic Pathfinding Lab. With over a decade of experience in semiconductor technology and a PhD in a related engineering field, I have developed a deep expertise in standard cell architecture, PDK generation, and the intricate balance of PPAC assessment. My background in researching advanced technology options for sub-2nm nodes aligns perfectly with your team's mission to push the boundaries of logic technology.
Throughout my career, I have successfully led projects involving library characterization and Place and Route optimization, ensuring that design rules and process capabilities are perfectly synchronized. I am particularly drawn to this role because of Samsung's leadership in semiconductor innovation and the opportunity to contribute to the knowledge transfer between the San Jose lab and the Technology Development team in Korea. I am confident that my collaborative approach and technical rigor will make me a valuable asset to your research initiatives.
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Откликнитесь в samsungsemiconductor уже сейчас
Присоединяйтесь к команде Samsung Semiconductor и определяйте будущее полупроводниковых технологий sub-2nm уже сегодня!
Описание вакансии
Please Note:
To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period.
Advancing the World’s Technology Together
Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you’ll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what’s possible and powering the future.
We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We’re dedicated to empowering people to be their true selves. Together, we’re building a better tomorrow for our employees, customers, partners, and communities.
What You’ll Do
We are looking for experienced technologists who will independently research and explore future logic technology paths, capabilities, and applications through design/system-technology optimization (DTCO).
The candidate will be a key technical member of the Logic Pathfinding Lab, part of the Samsung Semiconductor Inc (SSI) in San Jose. He or she will join a team of experts in researching and evaluating advanced technology options, and assisting in knowledge / technology transfer to the Samsung Logic Technology Development (TD) in Korea. The successful candidate will be responsible for researching and evaluating new device architectures, materials, and integration schemes through chip design metrics to meet the need of sub-2nm technology nodes. The candidate should have demonstrated skills and experience in standard cell architecture creation, logic cell library characterizations, Place and Route, Process Design Kit (PDK) generation, and a strong understanding of Logic process integration. The candidate should have excellent communication skills, and be able to collaborate with and guide multiple organizations, including research consortia.
Location: Daily onsite presence at our San Jose office/headquarters in alignment with our Flexible Work policy
Job ID: 42843
Reports to: Senior Director
- Create and optimize standard cell architecture and libraries to enable new device scheme and technology Performance, Power, Area, Cost (PPAC) assessment.
- Optimize DTCO collaterals to enable block-level design.
- Analyze technology design rules and process capabilities, and identify their impact on PPAC.
- Develop early DTCO methodologies to assess new technology options.
- Develop internal benchmarking capability based on available data, modeling, and/or learning from external sources, and create assessments to share with internal R&D teams.
- Collaborate and guide external vendors on DTCO development.
What You Bring
- PhD in Electrical Engineering, Mechanical Engineering, Chemical Engineering, Materials Science and Engineering, Computer Science, Physics or related fields and 10+ years of industry experience.
- Standard cell layout design and library generation skills.
- RTL synthesis, place and route, and timing analysis skills.
- DTCO modeling skills, from the logic standard cell to process design kit (PDK), including Library/Technology/Design Rule Check deck generation.
- SRAM bit-cell design and macro simulation skills is a strong plus.
- Understanding of power delivery network schemes.
- You’re inclusive, adapting your style to the situation and diverse global norms of our people.
- An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
- You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
- Innovative and creative, you proactively explore new ideas and adapt quickly to change.
#LI-SF1
What We OfferThe pay range below is for all roles at this level across all US locations and functions. Pay within this range varies by work location and may also depend on job-related knowledge, skills, and experience. We also offer incentive opportunities that reward employees based on individual and company performance.
This is in addition to our diverse package of benefits centered around the wellbeing of our employees and their loved ones. In addition to the usual Medical/Dental/Vision/401k, our inclusive rewards plan empowers our people to care for their whole selves. An investment in your future is an investment in ours.
Give Back With a charitable giving match and frequent opportunities to get involved, we take an active role in supporting the community.
Enjoy Time Away You’ll start with 4+ weeks of paid time off a year, plus holidays and sick leave, to rest and recharge.
Care for Family Whatever family means to you, we want to support you along the way—including a stipend for fertility care or adoption, medical travel support, and virtual vet care for your fur babies.
Prioritize Emotional Wellness With on-demand apps and free confidential therapy sessions, you’ll have support no matter where you are.
Stay Fit Eating well and being active are important parts of a healthy life. Our onsite Café and gym, plus virtual classes, make it easier.
Embrace Flexibility Benefits are best when you have the space to use them. That’s why we facilitate a flexible environment so you can find the right balance for you.
Base Pay Range
$189,000—$301,000 USD
Equal Opportunity Employment Policy
Samsung Semiconductor takes pride in being an equal opportunity workplace dedicated to fostering an environment where all individuals feel valued and empowered to excel, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status.
When selecting team members, we prioritize talent and qualities such as humility, kindness, and dedication. We extend comprehensive accommodations throughout our recruiting processes for candidates with disabilities, long-term conditions, neurodivergent individuals, or those requiring pregnancy-related support. All candidates scheduled for an interview will receive guidance on requesting accommodations.
Recruiting Agency Policy
We do not accept unsolicited resumes. Only authorized recruitment agencies that have a current and valid agreement with Samsung Semiconductor, Inc. are permitted to submit resumes for any job openings.
Applicant AI Use Policy
At Samsung Semiconductor, we support innovation and technology. However, to ensure a fair and authentic assessment, we prohibit the use of generative AI tools to misrepresent a candidate's true skills and qualifications. Permitted uses are limited to basic preparation, grammar, and research, but all submitted content and interview responses must reflect the candidate’s genuine abilities and experience. Violation of this policy may result in immediate disqualification from the hiring process.
Applicant Privacy Policy
https://semiconductor.samsung.com/about-us/careers/us/privacy/
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Навыки
- DTCO
- PDK
- Standard Cell Design
- RTL Synthesis
- Place and Route
- Timing Analysis
- SRAM Design
- Library Characterization
- Process Integration
- PPAC Analysis
Возможные вопросы на собеседовании
Проверка понимания ключевой метрики эффективности в дизайне чипов.
Как вы подходите к анализу компромиссов PPAC (Power, Performance, Area, Cost) при оценке новых архитектур транзисторов для узлов sub-2nm?
Оценка практического опыта в создании инфраструктуры проектирования.
Опишите ваш опыт разработки и оптимизации PDK (Process Design Kit) и то, как вы обеспечиваете точность DRC-правил на ранних этапах разработки техпроцесса.
Проверка навыков работы с инструментами проектирования.
Какие основные сложности возникают при синтезе RTL и Place and Route для стандартных ячеек с экстремально высокой плотностью упаковки?
Оценка способности работать в распределенной исследовательской среде.
Расскажите о случае, когда вам приходилось передавать сложные технологические решения между исследовательскими центрами или внешними вендорами. Как вы обеспечивали точность передачи знаний?
Проверка дополнительных навыков, указанных как плюс.
Каков ваш опыт в проектировании SRAM bit-cell и как оптимизация на уровне ячейки памяти влияет на общую стратегию DTCO для логического техпроцесса?
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