- Страна
- США
- Зарплата
- 100 000 $ – 500 000 $
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Formal Verification Engineer
Tenstorrent — один из самых перспективных стартапов в сфере ИИ-железа с сильной командой. Высокий уровень компенсации и работа над передовыми технологиями делают эту вакансию крайне привлекательной.
Сложность вакансии
Роль требует глубоких знаний в математической логике, архитектуре процессоров RISC-V и владения специализированными EDA-инструментами. Высокая сложность обусловлена необходимостью верификации сложнейших ИИ-чиплетов и систем на кристалле.
Анализ зарплаты
Предлагаемый диапазон $100k - $500k крайне широк, так как охватывает позиции от Junior до Lead. Для рынка США (Санта-Клара/Остин) медиана в $220k является конкурентной для Senior-уровня, а верхняя граница значительно превышает средние рыночные показатели, включая опционы.
Сопроводительное письмо
I am writing to express my strong interest in the Formal Verification Engineer position at Tenstorrent. With a deep background in hardware verification and a passion for pushing the boundaries of formal methods, I have closely followed Tenstorrent’s innovations in RISC-V CPU architecture and AI acceleration. My experience in applying SVA and tools like JasperGold to sign off complex digital logic aligns perfectly with your mission to build high-performance, reliable AI platforms.
Throughout my career, I have focused on bridging the gap between architectural specifications and RTL implementation through rigorous formal proofs. I am particularly excited about Tenstorrent's approach to unifying software models and semiconductors, and I am eager to contribute to your formal verification strategy. I am confident that my technical expertise in temporal logic and my collaborative approach to solving intricate logic bugs will be an asset to your world-class engineering team.
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Откликнитесь в tenstorrent уже сейчас
Присоединяйтесь к команде Tenstorrent и создавайте будущее ИИ-процессоров с помощью передовых методов формальной верификации!
Описание вакансии
Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities.
As a Formal Verification Engineer at Tenstorrent, you will be at the forefront of applying advanced formal verification methods to thoroughly verify intricate CPUs and chiplets. This role involves driving the formal verification strategy, mentoring engineers, and fostering cross-team collaboration to uphold rigorous quality standards and functional specifications. Your direct contributions will be vital to developing groundbreaking technologies and ensuring their seamless and efficient operation.
This role ishybrid, based out of Santa Clara, CA, Austin, TX, or Bangalore, IN.
We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting.
Who You Are
- A formal methods practitioner who enjoys pushing the boundaries of formal methods to solve difficult verification problems.
- Demonstrated experience in applying formal methods to sign off designs or sub-components of designs.
- Detail-oriented with a desire to overcome complex challenges.
- Comfortable collaborating across design, microarchitecture, and verification teams to identify subtle logic bugs.
- Possess strong communication and excellent interpersonal skills for effective team collaboration.
What We Need
- Lead with 5+ years of hands-on experience in formal methods applied to hardware verification.
- B.S. or M.S. (or higher degree) in Computer Engineering, Electrical Engineering, or Mathematics with 5+ years of relevant work experience.
- Strong background and hands-on experience with formal methods and their application to hardware, software, or systems.
- Hands-on experience with VLSI, digital logic design, and verification techniques. Knowledge of digital logic is required.
- Proficiency in temporal logic assertion-based languages like SVA or PSL.
- Experience using EDA formal tools such as Jasper, VC-Formal, Questa, or Yosys for property checking and formal regression. Tool development experience is a plus.
What You Will Learn
- Leverage formal verification algorithms and techniques to prove correctness and identify bugs in design specifications and RTL for high-performance CPUs and chiplets.
- Collaborate with architects to develop formal micro-architecture and architectural specifications for intricate designs, including crafting innovative solutions for complex challenges.
- Prove the robustness of complex design micro-architectures.
- Architect correct-by-construction design methodologies to enhance formal verification efficiency and productivity and contribute to the evolution of formal methodologies.
- Apply artificial intelligence techniques to improve specifications, formal methods applications, and formal verification.
- Contribute to cross-functional product development across CPU, AI, and interconnect domains, and with partners.
Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.
Tenstorrent offers a highly competitive compensation package and benefits, and we are an equal opportunity employer.
This offer of employment is contingent upon the applicant being eligible to access U.S. export-controlled technology. Due to U.S. export laws, including those codified in the U.S. Export Administration Regulations (EAR), the Company is required to ensure compliance with these laws when transferring technology to nationals of certain countries (such as EAR Country Groups D:1, E1, and E2). These requirements apply to persons located in the U.S. and all countries outside the U.S. As the position offered will have direct and/or indirect access to information, systems, or technologies subject to these laws, the offer may be contingent upon your citizenship/permanent residency status or ability to obtain prior license approval from the U.S. Commerce Department or applicable federal agency. If employment is not possible due to U.S. export laws, any offer of employment will be rescinded.
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Навыки
- Computer Architecture
- RTL
- Formal Verification
- RISC-V
- Questa
- SVA
- PSL
- JasperGold
- VC-Formal
- Yosys
- Digital Logic Design
- VLSI
Возможные вопросы на собеседовании
Проверка базовых знаний временной логики, критически важных для написания свойств.
Объясните разницу между операторами '|->' и '|=>' в SystemVerilog Assertions (SVA) и приведите пример использования каждого.
Формальная верификация часто сталкивается с проблемой взрыва состояний; важно знать, как кандидат справляется с этим.
Какие стратегии вы используете для борьбы с проблемой пространства состояний (state space explosion) при верификации сложных блоков?
Оценка практического опыта работы с индустриальными инструментами.
Опишите ваш опыт работы с JasperGold или VC-Formal: какие типы абстракций вы применяли для достижения сходимости (convergence)?
Понимание архитектуры процессоров необходимо для эффективной верификации.
Как бы вы подошли к формальной верификации конвейера команд (instruction pipeline) на предмет отсутствия тупиковых ситуаций (deadlocks)?
Вакансия упоминает использование ИИ для улучшения спецификаций.
Как, по вашему мнению, методы машинного обучения могут быть интегрированы в процесс формальной верификации для повышения его эффективности?
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- Страна
- США
- Зарплата
- 100 000 $ – 500 000 $