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IC Package Engineer (Starlink/Akoustis)

Оценка ИИ

Работа в SpaceX над проектом Starlink — это уникальный шанс участвовать в создании глобальной инфраструктуры будущего. Высокий престиж компании компенсирует требования к переработкам и строгие правила ITAR.


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Сложность вакансии

ЛегкоСложно
Оценка ИИ

Позиция требует глубоких знаний в материаловедении и микроэлектронике, а также готовности к интенсивному графику работы. Высокая планка ответственности обусловлена работой с критически важным оборудованием для Starlink.

Анализ зарплаты

Медиана115 000 $
Рынок95 000 $ – 145 000 $
Оценка ИИ

Зарплата для инженеров по корпусированию ИС в Техасе (район Остина/Бастропа) обычно конкурентоспособна, а SpaceX часто предлагает пакеты с акциями, что значительно повышает общий доход. Указанный рыночный диапазон отражает базовые оклады для специалистов с опытом от 1-3 лет.

Сопроводительное письмо

I am writing to express my strong interest in the IC Package Engineer position at SpaceX, specifically within the Starlink/Akoustis team. With a solid foundation in materials science and hands-on experience in semiconductor packaging technologies such as flip-chip, wire bonding, and WLP, I am eager to contribute to the development of high-reliability electronics that power the world's most advanced satellite constellation.

Throughout my career and academic projects, I have developed a deep understanding of thermal management and reliability testing standards like JEDEC and IPC. My proficiency in AutoCAD for mechanical layout, combined with a data-driven approach to failure analysis and FMEA, aligns perfectly with SpaceX's mission of maintaining a tight feedback loop and high-speed deliverables. I am particularly drawn to SpaceX’s culture of in-house innovation and am ready to tackle the complex challenges of package-board integration for mission-critical applications.

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Составьте идеальное письмо к вакансии с ИИ-агентом

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Откликнитесь в spacex уже сейчас

Присоединяйтесь к SpaceX и создавайте будущее межпланетной связи, разрабатывая передовые решения для Starlink!

Описание вакансии

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.

IC PACKAGE ENGINEER (STARLINK/AKOUSTIS)

Akoustis is now operating as a wholly owned subsidiary of SpaceX, providing industry leading RF filters using patented XBAW technology to help drive the mission of making human life multi-planetary and connecting the world through Starlink. We design, build, launch, and operate the world's largest constellation of satellites, enabling us to operate a global internet network unbounded by traditional ground infrastructure limitations. The root of SpaceX’s success so far lies in our mission to keep all engineering and production in-house, which enables a tight feedback loop, nimble decision-making, and speedy deliverables. With millions of daily users worldwide already online, Starlink is truly a game-changer and levels the playing field for those who were previously unconnected.

We are looking for a highly skilled and motivated IC Package Engineer to lead the development, qualification, and implementation of advanced integrated circuit (IC) packaging solutions. In this role, you’ll play a critical part in enabling high-reliability, high-performance electronics for cutting-edge applications. You will work cross-functionally with design, manufacturing, reliability, supply chain, and failure analysis teams to deliver optimized semiconductor packaging that meets stringent thermal, mechanical, and electrical requirements. The ideal candidate will bring hands-on experience in semiconductor packaging, materials science, and electronics manufacturing processes, with a passion for technical innovation and attention to detail.

RESPONSIBILITIES:

  • Design, develop, and qualify IC packaging technologies including flip-chip, wire bonding, wafer-level packaging (WLP), QFN, CSP, and LGA
  • Evaluate and select packaging materials (substrates, mold compounds, underfills, adhesives) based on thermal, mechanical, and electrical properties
  • Drive thermal management strategies within packages, including simulation and implementation of heat dissipation techniques
  • Define and execute reliability test plans (e.g., thermal cycling, uHAST, HTOL) for qualification of package designs
  • Utilize EDA/CAD tools (e.g., AutoCAD) for mechanical layout, with experience in ANSYS or other simulation tools as a plus
  • Apply DFM methodologies to ensure manufacturability, reliability, and testability from concept through production
  • Provide technical guidance for IC assembly and packaging processes, including SMT, die attach, reflow, wire bonding, underfill, and encapsulation
  • Conduct and support failure analysis investigations using tools like X-ray, SEM, FIB, and cross-sectioning to drive root cause and corrective actions
  • Perform root cause analysis and data-driven troubleshooting using tools such as FMEA, SPC, and Six Sigma methodologies
  • Collaborate with PCB and substrate design teams to ensure co-design compatibility and package-board integration
  • Own project timelines, risks, and deliverables related to packaging initiatives and report progress to key stakeholders

BASIC QUALIFICATIONS:

  • Bachelor’s degree in mechanical Engineering, packaging Engineering, materials science, electrical Engineering, or or other engineering discipline
  • 1+ year of experience designing, qualifying, or implementing IC packaging solutions (internships and academic projects are applicable)

PREFERRED QUALIFICATIONS:

  • 2+ years of hands-on experience with semiconductor packaging technologies, including:

+ Flip-chip, wire bond, WLP, LGA, CSP, QFN

+ Organic/inorganic substrates and PCB manufacturing

  • Deep understanding of packaging materials and their thermal, mechanical, and electrical properties
  • Familiarity with thermal management techniques for power-dense or mission-critical electronics
  • Experience with reliability testing, including JEDEC and IPC standards (e.g., thermal cycling, uHAST, HTS, vibration)
  • Knowledge of assembly processes: SMT, die attach, reflow soldering, encapsulation, underfill, etc.
  • Strong analytical skills with expertise in:

+ Root Cause Analysis

+ Statistical Process Control (SPC)

+ Six Sigma / Lean tools

+ Failure Mode and Effects Analysis (FMEA)

  • Experience with EDA/CAD tools such as AutoCAD (required); ANSYS or COMSOL (a plus)
  • Proven ability to lead cross-functional efforts across design, reliability, manufacturing, and supply chain
  • Strong project management, organizational, and communication skills

ADDITIONAL REQUIREMENTS:

  • Must be willing to work extended hours and weekends as needed to meet critical milestones
  • Ability to travel up to 20% domestically and internationally for supplier and manufacturing support
  • Ability to perform light physical tasks (lifting up to 25 lbs, handling packaging samples)

ITAR REQUIREMENTS:

  • To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR here.

SpaceX is an Equal Opportunity Employer; employment with SpaceX is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.

Applicants wishing to view a copy of SpaceX’s Affirmative Action Plan for veterans and individuals with disabilities, or applicants requiring reasonable accommodation to the application/interview process should reach out to EEOCompliance@spacex.com.

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Навыки

  • IC Packaging
  • Flip Chip
  • Wire Bonding
  • Wafer-level Packaging
  • QFN
  • LGA
  • AutoCAD
  • Ansys
  • COMSOL
  • FMEA
  • Six Sigma
  • Statistical Process Control
  • Failure Analysis
  • SMT
  • Materials Science

Возможные вопросы на собеседовании

Проверка технических знаний основных типов корпусирования, упомянутых в вакансии.

Можете ли вы сравнить преимущества и недостатки Flip-chip и Wire Bonding для высокочастотных RF-приложений?

Оценка навыков решения проблем и владения инструментами анализа отказов.

Опишите ваш опыт проведения анализа первопричин (RCA) при обнаружении дефекта в процессе сборки микросхем.

Термоменеджмент критичен для спутниковых систем.

Какие стратегии отвода тепла вы бы предложили для плотно упакованного QFN корпуса в условиях ограниченного пространства?

Проверка понимания стандартов надежности.

Каков ваш опыт работы со стандартами JEDEC, в частности, при проведении тестов uHAST и термоциклирования?

Оценка соответствия культуре SpaceX (высокая скорость и итеративность).

Как вы расставляете приоритеты, когда сталкиваетесь с необходимостью одновременного решения проблем на производстве и проектирования новых решений?

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