- Страна
- США
- Зарплата
- 125 000 $ – 175 000 $
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RTL Design Engineer (Silicon Engineering)
Исключительная возможность работать в одной из самых инновационных компаний мира над проектом глобального масштаба. Высокая заработная плата дополняется акциями компании и отличным соцпакетом, хотя работа может требовать сверхурочных усилий.
Сложность вакансии
Высокая сложность обусловлена строгими требованиями ITAR (гражданство США или Green Card), необходимостью глубоких знаний в области микроархитектуры и готовностью к работе в интенсивном режиме SpaceX. Роль требует междисциплинарного взаимодействия и участия во всех этапах жизненного цикла разработки чипов.
Анализ зарплаты
Предлагаемая зарплата ($125k - $175k) полностью соответствует рыночным стандартам для инженеров по проектированию ASIC в Калифорнии. С учетом бонусов и акций SpaceX, совокупный доход может значительно превышать средние показатели по рынку.
Сопроводительное письмо
I am writing to express my strong interest in the RTL Design Engineer position within the Silicon Engineering team at SpaceX. With a solid foundation in SystemVerilog and experience in the full ASIC/FPGA design lifecycle, I am eager to contribute to the development of next-generation hardware for the Starlink satellite constellation. My background in implementing complex IP and participating in architectural discussions aligns perfectly with your mission to expand global connectivity.
Throughout my experience, I have developed a deep understanding of digital communication system datapath blocks and AXI/AHB protocols. I am particularly drawn to SpaceX's fast-paced, cross-functional environment where innovation is a daily requirement. I am confident that my technical skills in RTL design and my proactive approach to problem-solving will allow me to make immediate contributions to the Starlink program and help maximize its utility for users worldwide.
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Откликнитесь в spacex уже сейчас
Присоединяйтесь к команде SpaceX и создавайте чипы, которые обеспечат интернетом всю планету и помогут человечеству достичь Марса!
Описание вакансии
SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.
RTL DESIGN ENGINEER (SILICON ENGINEERING)
At SpaceX we’re leveraging our experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system. Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We’ve only begun to scratch the surface of Starlink’s potential global impact and are looking for best-in-class engineers to help maximize Starlink’s utility for communities and businesses around the globe.
We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation FPGAs and ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.
RESPONSIBILITIES:
- Design ASICs and/or FPGAs for Starlink projects, implementing IP for complex SoCs and participate in integration tasks using Verilog/SystemVerilog
- Participate in the full ASIC/FPGA design lifecycle for Starlink projects, from high-level conceptual and architectural discussions through microarchitecture, design partitioning, and collaboration with backend/implementation teams, and assist in lab bring-up and validation
- Engage in high-level architectural design for FPGA and ASICs
- Collaborate with cross-functional engineers in developing new technologies for the Starlink program impacting User terminals, Satellites, and more
BASIC QUALIFICATIONS:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or Physics
- 1+ years of experience in RTL Design using SystemVerilog, Verilog or VHDL
PREFERRED SKILLS AND EXPERIENCE:
- Master’s in Electrical/Computer Engineering or related field
- ASIC/FPGA system integration experience
- Proficiency in Python for scripting
- Experience in designing DSP or digital communication system datapath blocks
- Experience with EDA tools such as HDL simulators
- Experience and understanding of AXI/AHB/APB protocols
- Strong foundation in electrical engineering fundamentals
- Ability to work in a dynamic environment with changing needs and requirements
- Team-player, can-do attitude and ability to work well in a group environment while still contributing on an individual basis
- Demonstrated ability to work in a highly cross-functional role
- Enjoys being challenged and learning new skills
ADDITIONAL REQUIREMENTS:
- Ability to work extended hours or weekends as needed for mission critical deadlines
COMPENSATION & BENEFITS:
Pay range:
ASIC Design Engineer/Level I: $125,000.00 - $145,000.00/per year
ASIC Design Engineer/Level II: $140,000.00 - $175,000.00/per year
Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.
Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation & will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year.
ITAR REQUIREMENTS:
- To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR here.
SpaceX is an Equal Opportunity Employer; employment with SpaceX is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.
Applicants wishing to view a copy of SpaceX’s Affirmative Action Plan for veterans and individuals with disabilities, or applicants requiring reasonable accommodation to the application/interview process should reach out to EEOCompliance@spacex.com.
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Навыки
- SystemVerilog
- Verilog
- VHDL
- RTL Design
- ASIC
- FPGA
- Python
- DSP
- AXI
- AHB
- APB
- EDA
Возможные вопросы на собеседовании
Проверка фундаментальных знаний цифровой логики, критически важных для RTL-дизайна.
Объясните разницу между блокирующими и неблокирующими присваиваниями в SystemVerilog и приведите примеры их использования.
SpaceX ищет инженеров, способных оптимизировать дизайн под конкретные задачи Starlink.
Как бы вы подошли к оптимизации энергопотребления и площади кристалла при проектировании блока обработки сигналов (DSP) для спутника?
Работа с протоколами передачи данных — ключевая часть обязанностей.
Опишите структуру транзакции в протоколе AXI. Какие преимущества он дает по сравнению с более простыми протоколами вроде APB?
Проверка навыков отладки и работы с оборудованием.
Расскажите о вашем опыте bring-up и валидации чипа в лаборатории. С какими самыми сложными проблемами вы сталкивались при тестировании на реальном железе?
Оценка способности работать в условиях жестких дедлайнов и меняющихся требований.
Приведите пример ситуации, когда вам приходилось быстро осваивать новую технологию или менять архитектурное решение из-за изменения требований проекта.
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- Страна
- США
- Зарплата
- 125 000 $ – 175 000 $