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- США
- Зарплата
- 189 000 $ – 301 000 $
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Senior Manager, Serdes Analog Design
Исключительная позиция в компании-лидере индустрии с очень конкурентной заработной платой и отличным пакетом льгот. Работа над передовыми технологиями (224/448Gbps) обеспечивает профессиональный рост, хотя требование работы в офисе 5 дней в неделю может подойти не всем.
Сложность вакансии
Высокая сложность обусловлена требованиями к огромному опыту (10-15+ лет) в узкоспециализированной области проектирования Serdes и необходимостью глубоких знаний передовых техпроцессов CMOS. Роль совмещает в себе как экспертное проектирование схем, так и управленческие функции по руководству командой дизайнеров.
Анализ зарплаты
Предложенный диапазон $189k – $301k полностью соответствует рыночным стандартам для позиций Senior Manager в области Analog Design в Сан-Хосе. Верхняя граница диапазона даже несколько превышает средние показатели, что характерно для Tier-1 технологических гигантов уровня Samsung.
Сопроводительное письмо
I am writing to express my strong interest in the Senior Manager, Serdes Analog Design position at Samsung Semiconductor. With over 15 years of experience in analog and mixed-signal design, including a deep focus on high-speed Serdes architectures, I am confident in my ability to lead your team in developing next-generation interconnect solutions. My technical background aligns perfectly with your requirements for expertise in CTLE, DFE, and clock distribution, as well as my hands-on experience with advanced CMOS process technologies.
Throughout my career, I have successfully led design teams from initial architecture definition through to silicon validation and debugging. I am particularly excited about Samsung's work on 224/448Gbps UA-link and Ethernet technologies, as these push the boundaries of what is possible in data center and hyperscale environments. I am a collaborative leader who thrives in innovative environments, and I am eager to bring my expertise in EDA tools like Cadence and Spectre, along with my passion for mentoring designers, to your San Jose office.
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Описание вакансии
Please Note:
To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period.
Advancing the World’s Technology Together
Our technology solutions power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you’ll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what’s possible and powering the future.
We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We’re dedicated to empowering people to be their true selves. Together, we’re building a better tomorrow for our employees, customers, partners, and communities.
We power the tools you use every day--including smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more with our technology solutions. Here, you’ll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what’s possible and powering the future.
We believe that innovation and growth are driven by an inclusive culture and a diverse workforce. We’re dedicated to empowering people to be their true selves. Together, we’re building a better tomorrow for our employees, customers, partners, and communities.
Location: Onsite at our San Jose office 5 days a week
What You’ll Do
In this role, you will actively work on architecture and circuits of high-speed interconnect transceiver (Serdes). You will help define circuits and architecture for Serdes IPs, clock generation as well as traditional analog circuits. You’ll supervise designers to deliver the complete design and to support silicon validation and debugging.
You’ll work with a team to develop high-performance and low-power serdes, including display interface, camera sensor interface, UCIe / die-to-die interconnect and 224/448Gbps UA-link/Ethernet using cutting-edge process technologies.
- Define architecture and circuits for serdes projects.
- Supervise designers to complete the project and to conduct silicon validation.
- Hands-on circuit design experience is a must.
- Familiarity with low-power and low-voltage analog and custom digital circuit components using advanced CMOS process technologies
- Translate component design specification to schematics. Build simulation test-benches to evaluate circuit performance, functionality, power consumption and reliability.
- Supervise layout of the complete project. Optimize layout to improve the power consumption and performance of circuits
What You Bring
- Bachelors with 15+ years, Masters with 13+ years or PhDs with 10+ years of experience.
- Minimum 7+ yrs experience in Analog/Serdes SoC design experience.
- Knowledge and experience with analog circuits/mixed signal circuits: such as bandgap, LDO, filters.
- Knowledge and experience with circuits of Serdes IPS: CTLE, DFE, FFE, clock distributions, PI, IQ generation.
- Knowledge of Serdes architecture and high-speed interconnect standard (USB, PCIe, UCIe)
- Knowledge and experience with ESD, PLL, clock generation, ADC, DAC is a big plus.
- Well-versed in EDA tools (Cadence, Spectre, Totem, EMX)
- Comfortable with scripting languages (Python, Matlab)
- You’re inclusive, adapting your style to the situation and diverse global norms of our people.
- An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding.
- You’re collaborative, building relationships, humbly offering support and openly welcoming approaches.
- Innovative and creative, you proactively explore new ideas and adapt quickly to change.
#LI-VL1
What We OfferThe pay range below is for all roles at this level across all US locations and functions. Pay within this range varies by work location and may also depend on job-related knowledge, skills, and experience. We also offer incentive opportunities that reward employees based on individual and company performance.
This is in addition to our diverse package of benefits centered around the wellbeing of our employees and their loved ones. In addition to the usual Medical/Dental/Vision/401k, our inclusive rewards plan empowers our people to care for their whole selves. An investment in your future is an investment in ours.
Give Back With a charitable giving match and frequent opportunities to get involved, we take an active role in supporting the community.
Enjoy Time Away You’ll start with 4+ weeks of paid time off a year, plus holidays and sick leave, to rest and recharge.
Care for Family Whatever family means to you, we want to support you along the way—including a stipend for fertility care or adoption, medical travel support, and virtual vet care for your fur babies.
Prioritize Emotional Wellness With on-demand apps and free confidential therapy sessions, you’ll have support no matter where you are.
Stay Fit Eating well and being active are important parts of a healthy life. Our onsite Café and gym, plus virtual classes, make it easier.
Embrace Flexibility Benefits are best when you have the space to use them. That’s why we facilitate a flexible environment so you can find the right balance for you.
Base Pay Range
$189,000—$301,000 USD
Equal Opportunity Employment Policy
Samsung Semiconductor takes pride in being an equal opportunity workplace dedicated to fostering an environment where all individuals feel valued and empowered to excel, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status.
When selecting team members, we prioritize talent and qualities such as humility, kindness, and dedication. We extend comprehensive accommodations throughout our recruiting processes for candidates with disabilities, long-term conditions, neurodivergent individuals, or those requiring pregnancy-related support. All candidates scheduled for an interview will receive guidance on requesting accommodations.
Recruiting Agency Policy
We do not accept unsolicited resumes. Only authorized recruitment agencies that have a current and valid agreement with Samsung Semiconductor, Inc. are permitted to submit resumes for any job openings.
Applicant AI Use Policy
At Samsung Semiconductor, we support innovation and technology. However, to ensure a fair and authentic assessment, we prohibit the use of generative AI tools to misrepresent a candidate's true skills and qualifications. Permitted uses are limited to basic preparation, grammar, and research, but all submitted content and interview responses must reflect the candidate’s genuine abilities and experience. Violation of this policy may result in immediate disqualification from the hiring process.
Applicant Privacy Policy
https://semiconductor.samsung.com/about-us/careers/us/privacy/
Создайте идеальное резюме с помощью ИИ-агента

Навыки
- SerDes
- Analog Design
- CMOS
- Cadence
- Spectre
- Python
- MATLAB
- LDO
- PLL
- ADC
- DAC
- Mixed-Signal
- Layout Design
- Silicon Validation
Возможные вопросы на собеседовании
Проверка глубоких знаний архитектуры приемника для компенсации потерь в канале.
Можете ли вы подробно описать компромиссы между использованием CTLE и DFE при проектировании Serdes для скоростей выше 112 Гбит/с?
Оценка опыта работы с передовыми техпроцессами, упомянутыми в вакансии.
С какими основными проблемами целостности сигналов и надежности вы сталкивались при проектировании аналоговых блоков в техпроцессах 5нм и ниже?
Вакансия требует опыта руководства и доведения проекта до финальной стадии.
Опишите ваш опыт руководства командой при подготовке проекта к производству (tape-out). Как вы приоритизируете задачи при возникновении критических ошибок на этапе верификации?
Проверка знаний в области систем синхронизации, критически важных для Serdes.
Каковы ваши подходы к минимизации джиттера в распределительных сетях тактовых сигналов для многоканальных Serdes систем?
Оценка навыков отладки реального кремния, указанных в требованиях.
Расскажите о случае, когда результаты измерения параметров чипа (silicon validation) не совпали с результатами симуляции. Как вы локализовали проблему?
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