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Страна
США
Зарплата
150 000 $ – 180 000 $
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FPGA Simulation / Verification Engineer

Оценка ИИ

Привлекательная вакансия с высокой зарплатой и возможностью удаленной работы над значимыми проектами. Однако узкая специализация и строгие требования к гражданству США ограничивают круг кандидатов.


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Сложность вакансии

ЛегкоСложно
Оценка ИИ

Высокая сложность обусловлена требованием 10+ лет опыта и глубоких знаний стандарта DO-254 DAL A для критически важных систем. Работа предполагает владение сложным стеком UVM/SystemVerilog в контексте аэрокосмической отрасли.

Анализ зарплаты

Медиана165 000 $
Рынок145 000 $ – 190 000 $
Оценка ИИ

Предложенный диапазон $150k–$180k полностью соответствует рыночным ожиданиям для Senior/Lead FPGA Verification инженеров в США, особенно в оборонном секторе. Верхняя граница выше средней по рынку для удаленной работы в этом регионе.

Сопроводительное письмо

I am writing to express my strong interest in the FPGA Simulation / Verification Engineer position at Quest Defense Systems & Solutions. With over a decade of experience in FPGA verification and a deep mastery of SystemVerilog and UVM, I am confident in my ability to contribute to your complex aerospace data management platform. My background includes extensive work with DO-254 DAL A standards, ensuring that mission-critical designs meet the highest levels of safety and reliability.

Throughout my career, I have specialized in constructing scalable UVM testbenches, developing complex sequences, and performing rigorous code coverage analysis. I am particularly adept at troubleshooting RTL design flaws within simulation environments like QuestaSim and have a proven track record of delivering high-quality verification documentation, including test plans and trace matrices. I am excited about the opportunity to bring my technical expertise and problem-solving skills to the QDSS team and support your commitment to excellence in aerospace engineering.

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Присоединяйтесь к элите аэрокосмической инженерии и создавайте будущее безопасности вместе с QDSS!

Описание вакансии

![](https://www.jometer.com/v2/track?c=j9z3&a=2)

Unlock the power of Safety- and Mission-Critical Engineering with QDSS. We are seeking exceptional individuals to join our elite team- where your expertise will make an impact that matters. Elevate your career in a company dedicated to excellence and the pursuit of safety and mission success.

Quest Defense Systems & Solutions (QDSS) is supporting the verification of a complex aerospace data management platform and is looking for FPGA Simulation / Verification Engineers with strong UVM experience.

This role centers on developing and enhancing a SystemVerilog/UVM-based verification environment for safety-critical FPGA designs. You will work alongside a senior verification team to build scalable testbenches, develop sequences, debug RTL issues in simulation, and ensure compliance with DO-254 DAL A standards.

The ideal candidate brings deep hands-on experience in UVM testbench development, strong debugging skills, and a solid understanding of digital design and FPGA verification methodologies.

Due to the nature of the project, all applicants must be U.S. citizens.

This role is remote with a preference for candidates who live or are willing to relocate to Cedar Rapids, IA.

Required Qualifications:

  • Bachelor's Degree in electrical, computer or software engineering from an accredited college of university.
  • 10+ years of relevant FPGA Verification experience.
  • Ability to Construct FPGA Test Bench using UVM Components.
  • Deep experience with System Verilog
  • Experience with Sequence Development
  • Experience with developing DO-254 related documents including but not limited to: Test Plans, Test Procedures, Test Cases, Maintaining a Trace Matrix
  • Troubleshooting RTL Design Flaws using Simulation Environment.
  • Ability to take a problem and come up with a solution.
  • Familiarity with Unit level testbenches
  • Familiarity with Chip Level testbenches

Preferred Qualifications:

  • Experience developing UVM Predictors and Scoreboards to Implement Self-Checking Simulation Tests.
  • Familiarity with Register Modeling and Predicting Register Behavior.
  • Proficiency in developing UVM Agents, Drivers, Monitors, and Sequence Items.
  • Experience with Code Coverage Analysis for RTL Source (Statement, Branch, FSM, FSM Transition)
  • Experience in adoption and/or integration of emerging technologies (e.g., generative AI, automation platforms, digital assistants) into day-to-day operations for continuous improvement.

Technologies & Tools:

  • SVN
  • Mentor Graphics Questasim
  • Verilog
  • VHDL

The QDSS Advantage:

At QDSS, our advantage is purpose-driven work, collaborative teams, and complex challenges that push boundaries and build lasting impact. You’ll grow your career while contributing to mission-critical programs that demand excellence and shape the future.

What You’ll Find Here

  • Work That Matters – Next-generation, safety- and mission-critical projects where your contributions have real-world impact.
  • Growth That’s Supported – Competitive compensation, employer-matched 401(k), certification assistance, and clear opportunities for advancement.
  • A Culture That Works – A flexible, collaborative, and people-first environment where teamwork, innovation, and balance are valued.

Benefits Include

  • Competitive pay, comprehensive medical/dental/life and disability coverage, 401(k) with employer match, professional development support, and a flexible, friendly workplace.

Full compensation package is based on candidate experience and certifications

Pay Ranges

$150,000—$180,000 USD

At Quest Defense Systems and Solutions, we don’t just build technology — we engineer the future. From next-generation aerospace solutions to cutting-edge defense systems, we tackle the toughest, mission-critical challenges that keep people safe and push the boundaries of innovation. This is where problem-solvers, innovators, and visionary thinkers come together to shape the future. With over 25 years of aerospace and defense engineering expertise, our commitment to delivering high-quality, transformative solutions sets us apart — not just as an industry leader, but as a driving force for impactful change. Together, we’re not just leading the industry — we’re revolutionizing it.

Quest Defense provides equal employment opportunities to all employees and applicants for employment and prohibits discrimination and harassment of any type without regard to race, color, religion, age, sex, national origin, disability status, genetics, protected veteran status, sexual orientation, gender identity or expression, or any other characteristic protected by federal, state or local laws.

This policy applies to all terms and conditions of employment, including recruiting, hiring, placement, promotion, termination, layoff, recall, transfer, leaves of absence, compensation and training.The physical demands described here are representative of those that must be met by an employee to successfully perform the essential functions of this job. Reasonable accommodations may be made to enable individuals with disabilities to perform the essential functions.

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Создайте идеальное резюме с помощью ИИ-агента

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Навыки

  • FPGA
  • UVM
  • SystemVerilog
  • Verilog
  • VHDL
  • QuestaSim
  • DO-254
  • RTL Design
  • SVN
  • Simulation

Возможные вопросы на собеседовании

Проект связан с аэрокосмической отраслью, где соблюдение стандартов безопасности критично.

Опишите ваш опыт работы со стандартом DO-254. Какие специфические требования DAL A вы учитывали при разработке планов верификации?

UVM является ключевым требованием для этой роли.

Расскажите о наиболее сложной архитектуре UVM-тестбенча, которую вы разработали. Как вы реализовывали предикторы и скорборды для самопроверяющихся тестов?

Поиск ошибок в RTL — основная задача инженера по верификации.

Каков ваш подход к отладке сложных проблем в симуляции, когда поведение RTL не соответствует спецификации? Приведите пример из практики.

Покрытие кода гарантирует полноту тестирования.

Как вы используете анализ покрытия (Statement, Branch, FSM) для определения готовности дизайна к релизу? Что вы делаете, если 100% покрытие недостижимо?

Вакансия упоминает внедрение новых технологий.

Как вы видите применение генеративного ИИ или автоматизации в процессе верификации FPGA для повышения эффективности работы?

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