Principal Signal Integrity Engineer

Описание вакансии

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

At Astera Labs, we seek motivated Principal SI/PI and System Validation Engineers to work on our game-changing portfolio of connectivity products for Artificial Intelligence and Machine Learning applications. In this role, you will execute the SI planning, design, modeling, simulation, and lab validation with various system configurations. You will also formulate a comprehensive system validation plan and design experiments to root cause unexpected behavior, report results and specification compliance, and work with key internal customers to quantify margins and ensure robustness.

Basic Qualifications:

• Strong academic/technical background in electrical engineering; Bachelor’s is required; Master’s preferred.
• 8+ years of experience supporting or developing complex SoC/silicon products for Server, Storage, and Networking applications.
• 8+ years of hands-on high-speed SI/PI design, simulation, and measurement experience.
• We have a proven track record with defining hardware system constraints and high-speed technology roadmaps.
• Cross-functional design mentality with the silicon design community to develop systems.
• Self-starting, professional, and hands-on work ethic that can execute intense research in a dynamic environment.
• Proven track record solving problems independently, preferably as a tech lead.
• Entrepreneurial, open-minded behavior, and can-do attitude.
• Authorized to work in the US and start immediately.

Required experience:

• Familiar with SI and PI design challenges for high-speed interconnects
• Hardware product design experience in networking, compute, or RF.
• 2D and 3D simulation experience with Cadence/Mentor/Ansys/ADS/etc. toolsets
• EM modeling of connector structures
• High-speed SERDES measurement, channel simulation, and equalization
• Expertise in DDR4/5 memory bus designs
• Expertise in multi-level and NRZ signaling, COM, BER, jitter analysis
• Familiar with VNA, TDR, real-time and sub-sampling oscilloscopes, etc.
• Working knowledge of PCB fabrication limits and trade-offs
• PI experience a bonus.
• Familiar with industry-standard such as IEEE802.3
• Familiarity with PCIe5/6 and CXL specs, especially Electrical Compliance sections
• Working knowledge of key, high-speed design blocks such as PLLs, DFE, Tx EQ
• Experience in system testing, characterization, margin analysis, and optimization of high-speed PCIe/CXL data links over long and short channels
• In-depth understanding of DDR 4/5 protocols and JEDEC Standard. Hands-on experience with DDR4/5 post-silicon electrical validation.
• Proficiency in using high-speed lab equipment such as BERT, Oscilloscope, and VNA
• Strong debugging, analysis, and problem-solving skills with experience leading root cause and correction action teams. An inherent sense of urgency and accountability. Must have the ability to multi-task in a fast-paced environment.

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.